Magnetoelectronic devices, spin electronic devices, and spintronic devices are synonymous terms for devices that make use of effects predominantly caused by electron spin. Magnetoelectronics are used in numerous information devices to provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronics information devices include, but are not limited to, Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically an MRAM includes an array of magnetoressistive memory elements. Each magnetoresistive memory element typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers, such as a magnetic tunnel junction (MTJ), and exhibits an electrical resistance that depends on the magnetic state of the device. Information is stored as directions of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer are magnetically fixed or pinned, while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. Corresponding to the parallel and antiparallel magnetic states, the magnetic memory element has low (logic “0” state) and high (logic “1” state) electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive memory element, such as an MTJ device, to provide information stored in the magnetic memory element.
There are two completely different methods used to program the free layer: field switching and spin-torque switching. In field-switched MRAM, current carrying lines adjacent to the MTJ bit are used to generate magnetic fields that act on the free layer. In spin-torque MRAM, switching is accomplished with a current pulse through the MTJ itself. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. A reset current pulse will cause the final state to be parallel or logic “0”. A set current pulse, in the opposite polarity of the reset current pulse, will cause the final state to be antiparallel or logic “1”. Spin-torque transfer is known to occur in MTJ devices and giant magnetoresistance devices that are patterned or otherwise arranged so that the current flows substantially perpendicular to the interfaces, and in simple wire-like structures when the current flows substantially perpendicular to a domain wall. Any such structure that exhibits magnetoresistance has the potential to be a spin-torque magnetoresistive memory element.
Spin-torque MRAM (ST-MRAM), also known as spin-torque-transfer RAM (STT-RAM), is an emerging memory technology with the potential for non-volatility with unlimited endurance and fast write speeds at much higher density than field-switched MRAM. Since ST-MRAM switching current requirements reduce with decreasing MTJ dimensions, ST-MRAM has the potential to scale nicely at even the most advanced technology nodes. However, increasing variability in MTJ resistance and sustaining relatively high switching currents through bit cell select devices in both current directions can limit the scalability of ST-MRAM.
Referring to FIG. 1, a high ST-MRAM MTJ resistance variation and low magnetoresistance (MR) results in an overlapping distribution of resistances for high state bits 102 and low state bits 104. Known referenced read/sensing schemes using reference bits cannot distinguish high and low states successfully for 100% of the bits. Even if the number of bits in the overlapped region 101 is very low (or even zero), due to low MR and high resistance variation of the high and low state bits, a mid-point reference distribution can overlap with low or high state distributions causing read failure. Self-referenced read that references the bit being read/sensed to itself is known in the prior art to address the aforementioned sensing problem. For example, see U.S. Pat. No. 6,744,663 describing a destructive self-referenced read that requires 100% of the bits being read to be toggled or set to either high or low state during a read operation. The toggle or set to high state or reset to low state operation adds to read power consumption. And U.S. Patent Publication 2009/0323403 describes a non-destructive self-referencing read that does not have the full MR for sensing signal development resulting in a very low sensing signal.
Data stored in memory is defined in banks. A rank is a plurality of banks in a first direction (column) and a channel is a plurality of banks in a second direction (row). A process for accessing the memory comprises several clock cycles required for row and column identification and a read or write operation. The bandwidth for the data transfer may comprise a row of many thousands of bits.
FIG. 2 is a block diagram of an exemplary memory system 200 including a memory controller 202 that performs data transfer between a processor 204 and the memory 206. The memory controller 202 and the processor 204 may reside on the same chip 208, or they may reside on separate chips (not shown). The memory 206 comprises a non-volatile memory 218 using magnetic tunnel junctions, preferably ST-MRAM, for data storage. The non-volatile memory 218 comprises a plurality of non-volatile memory banks 228.
A control signal bus 232 provides control signals, such as chip select, row access strobe, column access strobe, and write enable, from the memory controller 202 to the non-volatile memory 218. An address bus 237 and a data line 240 couples the memory controller 202 to the non-volatile memory 218. Other control and clock signals may exist between the memory controller 202 and non-volatile memory 218 that are not shown in FIG. 2. Furthermore, an address bus 237, a control signal bus 232, and data line 240 may include multiple lines or bits.
In operation, an ACTIVATE operation for an address can be initiated in non-volatile memory 218. Subsequently, the memory controller 202 initiates READ or WRITE operations in the non-volatile memory 218. The data from non-volatile memory 218 is read after the non-volatile memory ACTIVATE operation is complete. Access to a bank in a double data rate (DDR) memory generally includes an ACTIVATE operation, followed by several READ/WRITE operations and a PRECHARGE operation. The ACTIVATE operation opens a row (or page) of typically 1,000 or more bits. The READ/WRITE operation performs the reading or writing of columns, e.g., 128 bits, in the open row. The PRECHARGE operation closes the row.
The ACTIVATE operation in DDR ST-MRAM performs a destructive self-referenced read where read data in the memory array is reset to logic state “0” during the read process. The read data from the array is stored in local data-store latches at the completion of the ACTIVATE operation. READ/WRITE operations subsequent to the ACTIVATE operation are performed to the local data-store latches instead of the ST-MRAM array. Small time interval, for e.g. 5 nanoseconds, between READ/WRITE operations is feasible due to fast latch operations.
The ACTIVATE operation can be initiated by an ACTIVATE command or any other command that performs the same operation. During a PRECHARGE operation, the data from local data-store latches are written back to the memory array, and as a result, that page is considered closed or not accessible without a new ACTIVATE operation. The PRECHARGE operation can be initiated by a PRECHARGE or AUTO-PRECHARGE command or any other command that performs the same operation. ACTIVATE operation in one bank may partially overlap with operations, such as ACTIVATE, PRECHARGE, READ, or WRITE, in other banks. The self-referenced sensing operation during ACTIVATE is susceptible to power supply noise from operations in other banks.
Accordingly, it is desirable to provide a self-referenced sense amplifier circuit for a ST-MRAM and a method of timing control signals and bias voltages thereto for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.